Dependency files track based compile target starting via include $(DEPS) condition doesn‘t allow to use dependencies at the fisrt project Makefile?

From the GNU Make docs GNU Make Automatic prerequisites : > The practice we recommend for automatic prerequisite generation is to have one makefile corresponding to each source file. For each source file name.c there is a makefile name.d which lists what files the object file name.o depends on. That way only the source files that have changed need to be rescanned to produce the new prerequisites. At my first project (executable generating) I have a such Makefile commands: all: server_supply $(BINARY) server_supply: $(SERVER_BINARY) $(SERVER_BINARY): make -C server -f Makefile all $(BINARY): $(OBJECTS) $(CC) -o $@ $(OBJECTS) -include $(DEPS) $(OBJECTS): %.o: %.cpp $(CC) $(CFLAGS) -c $< $(DEPFLAGS) $*.d -o $@ The problem is that this file‘s include statement prevents the second project (server) to recompile as it is considering by included $(DEPS) as up-to-date too. Is there any solution except one not to use dependencies at the first project-executable from the project group I'm working on? GitHub respotiory for the mmmaximum illustrativity