I'm using curl in my code and running through Makefile. but while running with "make" command its giving error like "curl/curl.h: No such file or directory". Here below is my makefile content. ` CXX = /home/directory/Documents/xyz/l4t-gcc/bin/aarch64-buildroot-linux-gnu-cc path = /home/directory/Documents/xyz/l4t-gcc/bin/ CFLAGS = -Wall #INCLUDE = -I/usr/local/include -I/usr/include -Iinclude #LDFLAGS = -L/usr/local/lib -I/usr/lib LDLIBS = -lcurl SOURCES = src/sms_wrapper.c src/twilio.c OUT = bin/sms_wrapper all: build build: $(SOURCES) $(CXX) -o $(OUT) $(CFLAGS) $(SOURCES) $(LDLIBS) clean: rm -rf bin/sms_wrapper ` I installed curl and added all things in Makefile which is needed for curl library. Does anyone have any suggestions or idea for resolving this thing !

I'm trying to use a makefile to bundle a combination of commands that should be run one after the other. Part of the make file looks like the following; .PHONY: dispersion all: dispersion -include make.in dispersion: phonopy --qe -d --dim='$(nx) $(ny) $(nz)' -c $(material)_primitive.in $(eval VAR=$(shell grep nat supercell.in)) echo $(VAR) basically, the first line creates a file called "supercell.in" and the second creates a variable called VAR that will be used in the subsequent lines. The above doesn't assign a value to the variable and I'm guessing this is due to the priority of the execution of lines. I would appreciate knowing a way around this problem.

All we get in Makefiles is just one %/$* [pattern rule](https://www.gnu.org/software/make/manual/html_node/Pattern-Rules.html#Pattern-Rules) pair.

$ cat Makefile
%.bla:; echo $*
$ make -s m.bla
m

How shortsighted of our Unix™ fathers.
How can I achieve something like %{0}.%{1}.bla that will give me

$ make -s a.b.bla
a b

Sure, one could use $(basename), $(suffix), $(subst), but I'm talking about two actual independent $*-like variables.

In the shell I can do

$ a=b b=c; eval echo \$$a
c

How do I do the same with GNU Make's $(eval) function?

$ cat Makefile
a=b
b=c
x:; echo {What goes here in order to get:}
$ make
c

I've inherited a major mess of a makefile network that was itself inherited from another project, with makefiles included all over the place. I'm trying to make a simple change without gutting the whole thing (tempting though that is, I just don't have the time right now). Is there any way to coax a full makefile out of gmake, *i.e.*, with all the included files already included? I know how to get the database dumped, but that's just about as hard to follow with all the extraneous junk that gets loaded in.

I have a Makefile, roughly so: .PRECIOUS: %.a %.b %.c %.a: touch $@ %.b: %.a touch $@ %.c: %.b touch $@ If I create "test.c" with a make test.c, all the 3 files (test.a, test.b, test.c) are created correctly. However, if I now remove test.a, and then I try to re-create test.c, then nothing happens. Reason is obvious: because test.c depends only on test.b, and test.b was not changed, not rebuild is needed. However, test.b should be rebuilt because test.a disappeared, and that should spread to test.c as well. I find this behavior as a highly un-intuitive side effect. Can I somehow let make to handle "transitive" dependencies on the intuitive way? (I.e. after the deletion of test.a, all the targets must be rebuilt.) The problem happens only with pattern rules. (P.s. I need all the intermediate files, this is why the PRECIOUS. Default behavior of the GNU Make is that it deletes the intermediary files.)

From the GNU Make docs GNU Make Automatic prerequisites : > The practice we recommend for automatic prerequisite generation is to have one makefile corresponding to each source file. For each source file name.c there is a makefile name.d which lists what files the object file name.o depends on. That way only the source files that have changed need to be rescanned to produce the new prerequisites. At my first project (executable generating) I have a such Makefile commands: all: server_supply $(BINARY) server_supply: $(SERVER_BINARY) $(SERVER_BINARY): make -C server -f Makefile all $(BINARY): $(OBJECTS) $(CC) -o $@ $(OBJECTS) -include $(DEPS) $(OBJECTS): %.o: %.cpp $(CC) $(CFLAGS) -c $< $(DEPFLAGS) $*.d -o $@ The problem is that this file‘s include statement prevents the second project (server) to recompile as it is considering by included $(DEPS) as up-to-date too. Is there any solution except one not to use dependencies at the first project-executable from the project group I'm working on? GitHub respotiory for the mmmaximum illustrativity

Is it possible to have a flexible extension for a prerequisite? For example, let's say I want to apply a rule to a list of targets that all have the same prerequisite pattern, except that some of them have a .xls extension, while the others have .xlsx. I'd like to allow for "%data.xlsx" OR "%data.xls" in the code below.

-make
target := */*report.html

$(target): %report.html: %report.qmd %data.xlsx
		quarto render $<

If it helps, I'm trying to re-compile all .qmd files in their respective directory; they result in .html files, and need data files that are either .xls, or .xlsx - job1/ - job1_report.html - job1_report.qmd - job1_data.xls - job2/ - job1_report.html - job2_report.qmd - job2_data.xlsx - ...

In someone's Makefile, I saw

clean:
	rm -f *.{log,pdf,bbl,blg,aux}

Upon running make clean, all the files were still there as before; nothing was removed. So what's the analogon of a shell's rm -f *.{log,pdf,bbl,blg,aux} in GNU Makefile? Do we really have to spell out $(RM) *.log *.pdf *.bbl *.blg *.aux in full? EDIT: I've been made aware that adding SHELL := /bin/bash to the top would do. Isn't there a more shell-independent way of removing all files with given extensions in the clean recipe of a Makefile?

I am creating a new makefile and I would like to create a set of utility functions which may be repetitively called. One of the functions is about how to return the parent path from any given path, e.g., return /some_folder from /some_folder/somefile. I can use subst and last word to extract the last word from the path. But I don't have a clue on how to exclude the last word. I would also like to find the common ancestor of two paths. Is there a general solution to such problems in makefile?

Here in make I want to make all targets in the whole Makefile depend on a specific file. (That specific file is Makefile in fact, because that's where I have all my formulas. But that's beside the point.) Here we see I have, like some nincompoop, painstakingly added it to each target,

$ grep Y Makefile
Y = Makefile
h32540000_zong.csv: $Y; $L | perl -pwle 'BEGIN{$$b=3; $$start=5;};$w; s/@\s+/\n/g;' > $@
h32540000_heng.csv: $Y; $L | perl -pwle \
h32540001_zong.csv: $Y; $L | perl -pwle 'BEGIN{$$start=8;};$w;$(\
h32540001_wall_zong.csv: $Y; $L | perl -wple \
h32540001_heng.csv: $Y; $L | perl -pwle \
h32540001_wall_heng.csv: $Y; $L | perl -pwle \

Is there some smarter way? Is there some

.ALL_TARGETS: Makefile #or,
%: Makefile

etc. notation I could use to achieve the same effect? Or maybe just have it operate on all targets that match a specific pattern? I was thinking of using the % notation, but alas that would reassign the command list of how to make each target...

I want to exclude all C files that have a matching asm file. The assembly files all have _x86_64.S at the end. The C files have identical names, but with .c instead of _x86_64.S at the end. How would I do something like: find . -not -name *{_x86_64.S but replace with .c} So, for example, if my_func.c and my_func_x86_64.S exist, then the file my_func.c will be excluded by the above command. Edit: The answer provided below works. I forgot to mention I was using this in a Makefile. What I had been doing was the following:

ASM_FILES = $(shell find ./src/assembly/x86_64/ -name "*.S" -printf "-not -name \"*%f*\" -and ")
ASM_INCLUDE += -wholename "./src/assembly/x86_64/*.S" -or
EXCLUDE += $(subst _x86_64.S,.c,$(ASM_FILES))

This works, but I was hoping for something a little cleaner.

Yes I read [Communicating Options to a Sub-'make'](https://www.gnu.org/software/make/manual/html_node/Options_002fRecursion.html) but I want to set an option for this make, not a sub-make, and set it within the Makefile, not via the command line.

$ cat Makefile
MAKEFLAGS = --warn-undefined-variables
zz: $(yy); xx
$ make -n # see, it didn't work!:
xx
$ make -n --warn-undefined-variables #need to do instead.
Makefile:2: warning: undefined variable 'yy'
xx
$ make --version
GNU Make 4.3

[Others](https://help-make.gnu.narkive.com/SzNl26tG/is-there-a-way-to-set-warn-undefined-variables-in-the-makefile) had the same problem too.

Isn't there some wildcard I can use for Make's .INTERMEDIATE target?

$ cat Makefile
.INTERMEDIATE: *.csv %.csv #failed
.INTERMEDIATE: north.csv g.csv #worked

Or must I list each and every file each and every time? Does any brand of Make allow wildcards here? The various manuals are not clear. The line above marked "worked" worked, as the matching files got removed.

Just touching file mod1.c, make should just recompile that source file, produce its correspondent object file, mod1.o, and should not recompile mod2.c, because the object file mod2.o will be still completely up to date (mod2.c is, as untouched, yet older than mod2.o, so no need to recompile). But I get the following behavior:
(This is not a personal creation, is from a written example from a source on make [saying the text that one will witness how make knows that mod2.c is untouched and will not recompile it]). **Makefile** $ cat Makefile SRC = mod1.c mod2.c main.c OBJ = mod1.o mod2.o main.o PROG = dbtest $(PROG): $(OBJ) gcc $(OBJ) -o $(PROG) $(OBJ): $(SRC)
**The problem:** $ make make: 'dbtest' is up to date. $ touch mod1.c $ make cc -c -o mod1.o mod1.c cc -c -o mod2.o mod2.c cc -c -o main.o main.c gcc mod1.o mod2.o main.o -o dbtest **Files contents** $ cat mod1.c #include void foo() { printf("Hello "); } $ cat mod2.c #include void bar() { printf(“World\n”); }
$ cat main.c #include void foo(); void bar(); int main (void) { foo(); bar(); return 0; }

Is there a known way to make Linux's make reject unintended use of GNU‑Make specific extensions in Makefile when editing or using other's Makefile in Linux? I mean, restricting GNU‑Make to behave as the [make specified in POSIX](http://pubs.opengroup.org/onlinepubs/009695399/utilities/make.html) and reject any GNU‑Make specific extensions? The .POSIX special target is not enough, according to “[4.9 Special Built-in Target Names (gnu.org)](https://www.gnu.org/software/make/manual/html_node/Special-Targets.html)” . The man page does not mention a command line option for this. Using another make utility may be an option. — **Update 2018-10-19** — I still have not found a direct answer to my question, but here is at least a document about this issue, a document which did not exist at the time I had this question: [A Tutorial on Portable Makefiles (nullprogram.com)](https://nullprogram.com/blog/2017/08/20/#may-your-makefiles-be-portable) .

I'm trying to organize a Makefile with complex commands into something more readable. I'm trying to break down a long list of parameters, but even single parameters are too bad, hence I wanted to break them too. But I cannot find a way to avoid unwanted spaces for these cases

# network and forward ports
QEMU_NET_FLAGS=-nic user
QEMU_NET_FLAGS+=,id=n1,restrict=on,ipv6=off,hostname=$(VMNAME)
# port forwards:
# hostfwd=[tcp|udp]:[hostaddr]:hostport-[guestaddr]:guestport
QEMU_NET_FLAGS+=,hostfwd=tcp::$(VMSSH)-:22
QEMU_NET_FLAGS+=,hostfwd=tcp::8000-:8000
QEMU_NET_FLAGS+=,hostfwd=tcp::8080-:8080
QEMU_NET_FLAGS+=,hostfwd=tcp::8081-:8081

Will cause -nic user ,id=1... instead of -nic user,id=1... ## Tried ::= First suggestion by @steeldriver:

QEMU_NET_FLAGS::=-nic user
QEMU_NET_FLAGS::=$(QEMU_NET_FLAGS),id=n1,restrict=on,ipv6=off,hostname=$(VMNAME)
QEMU_NET_FLAGS::=$(QEMU_NET_FLAGS),hostfwd=tcp::$(VMSSH)-:22

causes another problem since these are "templates", and variables like VMNAME and VMSSH should resolve late (recursively) when the resulting command line is used. And if I use :::= to then += values recursively, we are back to the unwanted space problem.

I am confused about the difference between them. I have read the GNU documentation, but I am still confused. > The value you specify is installed verbatim; if it contains references to other variables, these references are expanded whenever this variable is substituted (in the course of expanding some other string). When this happens, it is called recursive expansion. >The value of a simply expanded variable is scanned once, expanding any references to other variables and functions, when the variable is defined. Once that expansion is complete the value of the variable is never expanded again: when the variable is used the value is copied verbatim as the expansion. If the value contained variable references the result of the expansion will contain their values as of the time this variable was defined. Can anyone clearly explain their differences？ Thanks a lot.

For building u-boot of my board, I followed below two commands as told: $ sudo make nanopi_h3_defconfig ARCH=arm CROSS_COMPILE=arm-linux- $ sudo make ARCH=arm CROSS_COMPILE=arm-linux- I got the result from the 1st command: **configuration written to .config** It means success. But got the below from the 2nd command: make: arm-linux-gcc: No such file or directory /bin/sh: 1: arm-linux-gcc: not found dirname: missing operand Try 'dirname --help' for more information. scripts/kconfig/conf --silentoldconfig Kconfig ./scripts/binutils-version.sh: line 18: arm-linux-as: command not found CHK include/config.h CFG u-boot.cfg /bin/sh: 1: arm-linux-gcc: not found make: *** [scripts/Makefile.autoconf:79: u-boot.cfg] Error 1 make: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'. Stop. It seems trouble coming from arm-linux-gcc, but I ran command 'arm-linux-gcc', it works. So, why can the first command pass through arm-linux-gcc, but the 2nd command failed?

How do I send the output (stdout) to a log file from WITHIN the make file? I am NOT interested in a command line solution such as "make > build.log". Listed below is my generic make file. # +--------------------------------------------------------------------------+ # : Uncomment the appropriate section below (comment all others) : # +--------------------------------------------------------------------------+ # --- For TERMINAL program library files --- # LIBS := -lm # --- For RAYLIB program library files --- LIBS := -l:raylib/libraylib.a -lm # --- For NCURSES program library files --- # LIBS := -lform -lmenu -lncurses -lm # --- For SDL program library files --- # SDLALL := -lSDL2_image -lSDL2_mixer -lSDL2_net -lSDL2_ttf -lSDL2_gfx # LIBS := sdl2-config --libs --cflags $(SDLALL) -lm # ------------------------- End of user editable code ------------------------- DASH := " +--------------------------+" VERSION := " : Script: 2024.02.12 :" TARGET := " : For Raylib Makefiles :" AUTHOR := " : By: Jan W. Zumwalt :" # set compiler CC := gcc # additional header files HDRS := # additional include files INCS := # additional source files SRCS := main.c # name of executable EXEC := test # generate object file names OBJS := $(SRCS:.c=.o) # set compiler flags CFLAGS := -ggdb3 -O0 $(LIBS) --std=c17 -Wall # default recipe all: $(EXEC) # recipe for building final executable $(EXEC): $(OBJS) $(HDRS) $(INCS) Makefile > build.log $(CC) -o $@ $(OBJS) $(CFLAGS) make clean @echo $(\n) @echo $(DASH) @echo $(VERSION) @echo $(TARGET) @echo $(AUTHOR) @echo $(DASH) @echo $(\n) # recipe for building object files # $(OBJS): $(@:.o=.c) $(HDRS) Makefile # $(CC) -o $@ $(@:.o=.c) -c $(CFLAGS) # recipe to clean workspace clean: rm -f $(OBJS) # recipe to clean workspace test: test ./test .PHONY: all clean test